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march 2017 docid027498 rev 4 1 / 15 this is information on a product in full producti on. www.st.com STL120N4F6AG automotive - grade n - channel 40 v, 2.9 m typ., 55 a stripfet? f6 power mosfet in a powerflat? 5x6 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STL120N4F6AG 40 v 3.6 m 55 a ? aec - q101 qualified ? very low on - resistance ? very low gate charge ? high avalanche ruggedness ? low gate drive power loss ? wettable flank package applications ? switching applications description this device is an n - channel power mosfet developed usi ng the stripfet? f6 technology with a new trench gate structure. the resulting power mosfet exhibits very low r ds(on) in all packages. table 1: device summary order code marking package packaging STL120N4F6AG 120n4f6 powerflat? 5x6 tape and reel
contents STL120N4F6AG 2 / 15 docid027498 rev 4 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 powerflat? 5x6 wf type r package information .......................... 9 4.2 p owerflat? 5x6 wf packing information ................................ .... 12 5 revision history ................................ ................................ ............ 14
STL120N4F6AG electrical rat ings docid027498 rev 4 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 20 v v ds drain - source voltage 40 v i d (1) drain current (continuous) at t c = 25 c 55 a i d (1) drain current (continuous) at t c = 100 c 55 a i dm (2) drain current (pulsed) 220 a p tot total dissipation at t c = 25 c 115 w t stg storage temperature range - 55 to 175 c t j operating junction temperature range c notes: (1) drain current is limited by package, the current capability of the silicon is 120 a at 25 c . (2) pulse width is limited by safe operating area . table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 1.3 c/w r thj - pcb (1) thermal resistance junction - pcb 31.3 notes: (1) when mounted on 1 inch2 2 oz. cu board, t 10 s table 4: avalanche characteristics symbol parameter value unit i av avalanche current, repetitive or not repetitive (pulse width limited by maximum junction temperature) 20 a e as single pulse avalanche energy (t j = 25 c, i c = i av , v dd = 25 v) 200 mj
electrical characteristics STL120N4F6AG 4 / 15 docid027498 rev 4 2 electrical characteristics (t c = 25 c unless otherwise specified) table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 250 a 40 v i dss zero gate voltage drain current v gs = 0 v, v ds = 40 v 1 a v gs = 0 v, v ds = 40 v, tj = 125 c (1) 10 a i gss gate - body leakage current v ds = 0 v, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 13 a 2.9 3.6 m notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 v - 3700 - pf c oss output capacitance - 625 - pf c rss reverse transfer capacitance - 295 - pf q g total gate charge v dd = 20 v, i d = 26 a, v gs = 0 to 10 v (see figure 14: "test circuit for gate charge behavior" ) - 63 - nc q gs gate - source charge - 19 - nc q gd gate - drain charge - 15 - nc r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 1.5 - table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 20 v, i d = 13 a, r g = 4.7 , v gs = 10 v (see figure 13: "test circuit for resistive load switching times" and figure 18: "switching time waveform" ) - 20 - ns t r rise time - 70 - ns t d(off) turn - off - delay time - 40 - ns t f fall time - 20 - ns
STL120N4F6AG electrical characteristics docid027498 rev 4 5 / 15 table 8: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 55 a i sdm (1) source - drain current (pulsed) - 220 a v sd (2) forward on voltage v gs = 0 v, i sd = 13 a - 1.1 v t rr reverse recovery time i sd = 26 a, di/dt = 100 a/s, v dd = 25 v (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 40 ns q rr reverse recovery charge - 5.6 nc i rrm reverse recovery current - 2.8 a notes: (1) pulse width is limited by safe operating area . (2) pulse test: pulse duration = 300 s, duty cycle 1.5%
electrical characteristics STL120N4F6AG 6 / 15 docid027498 rev 4 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STL120N4F6AG electrical characteris tics docid027498 rev 4 7 / 15 figure 8 : capacitance variations figure 9 : normalized v (br)dss vs temperature figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized on - resistance vs. temperature figure 12 : source - drain diode forward characteristics
test circuits STL120N4F6AG 8 / 15 docid027498 rev 4 3 test circuits figure 13 : test circuit for resistive load switching times figure 14 : test circuit for gate charge behavior figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : switching time waveform
STL120N4F6AG package information docid027498 rev 4 9 / 15 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade de finitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 powerflat? 5x6 wf type r package information figure 19 : powerflat? 5x6 wf type r package outline a0y5_8231817_r_wf_rev_14
package information STL120N4F6AG 10 / 15 docid027498 rev 4 table 9: powerflat? 5x6 wf type r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 c 5.80 6.00 6.10 d 5.00 5.20 5.40 d2 4.15 4.45 d3 4.05 4.20 4.35 d4 4.80 5.00 5.10 d5 0.25 0.4 0.55 d6 0.15 0.3 0.45 e 1.27 e 6.20 6.40 6.60 e2 3.50 3.70 e3 2.35 2.55 e4 0.40 0.60 e5 0.08 0.28 e6 0.20 0.325 0.45 e7 0.85 1.00 1.15 e9 4.00 4.20 4.40 e10 3.55 3.70 3.85 k 1.275 1.575 l 0.725 0.825 0.925 l1 0.175 0.275 0.375 ? 0 12
STL120N4F6AG package information docid027498 rev 4 11 / 15 figure 20 : powerflat? 5x6 recommended footprint (dimensions are in mm) 8231817_footprint_rev14
package information STL120N4F6AG 12 / 15 docid027498 rev 4 4.2 powerflat? 5x6 wf packing information figure 21 : powerflat? 5x6 wf tape (dimensions are in mm) figure 22 : powerflat? 5x6 package orientation in carrier t ape
STL120N4F6AG package information docid027498 rev 4 13 / 15 figure 23 : powerflat? 5x6 reel (dimensions are in mm)
revision history STL120N4F6AG 14 / 15 docid027498 rev 4 5 revision history table 10: document revision history date revision changes 19 - feb - 2015 1 first release. 11 - apr - 2016 2 updated table 2: "absolute maximum ratings" minor text changes. 10 - jan - 2017 3 updated table 2: "absolute maximum ratings" and table 8: "source drain diode" . updated figure 6: "gate charge vs gate - source voltage" and figure 8: "capacitance variations" . minor text changes 0 9 - mar - 2017 4 updated table 2: "absolute maximum ratings" and table 3: "thermal data" . updated figure 2: "safe operating area" , figure 3: "thermal impedance" and figure 8: "capacitance variations" . added figure 9: "normalized v(br)dss vs temperature" and figure 10: "normalized gate threshold voltage vs temperature" . minor text changes
STL120N4F6AG docid027498 rev 4 15 / 15 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics C all rights reserved

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